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Связанные издания:

Address Register Assignment for Reducing Code Size
A New Fast Algorithm for Optimal Register Allocation in Modulo Scheduled Loops
A Novel High-Speed Memory Organization for Fine-Grain Multi-Thread Computing
A RISC Processor Architecture with a Versatile Stack System
A VLIW Architecture Based on Shifting Register Files
Code Scheduling for VLIW/Superscalar Processors with Limited Register Files
Cooperating/Distributed Grammar Systems with Registers: the Regular Case
Deductive formal verification of search programs in arrays of arbitrary size for abstract register machines
Die Hardwarebeschreibungssprache KARL II. Sprachbeschreibung
Early Control of Register Pressure for Software Pipelined Loops
Efficient Register Allocation for Large Basic Blocks
Exploting Instruction-Level Parallelism with the Conjugate Register File Scheme
Generating Designs Using an Algorithmic Register Transfer Language with Formal Semantics
How a Rainbow Coloring Function Can Simulate Wait-Free Handshaking
Inside the Microsoft Windows 98 Registry
KARL-II eine Sprache zur Spezifikation beim Entwurf Kunden-spezifischer Digitalbausteine
Linear Scan Register Allocation in the Context of SSA Form and Register Constraints
Minimum Register Instruction Scheduling: A New Approach for Dynamic Instruction Issue Processors
Register Pipelining: An Integrated Approach to Register Allocation for Scalar and Subscripted Variables
Register Promotion in C Programs
Register Renaming and Dynamic Speculation: An Alternative Approach
Register Saturation in Superscalar and VLIW Codes
Register Traffic Analysis for Streamlining Inter-Operation Communication in Fine-Grain Parallel Processors
Removing Anti Dependences by Repairing
Selective Register Renaming: A Compiler-Driven Approach to Dynamic Register Renaming
Software-Directed Register Deallocation for Simultaneous Multithreaded Processors
Toward Zero-Cost Branches Using Instruction Registers