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Связанные издания:

A Comparison of Modulo Scheduling Techniques for Software Pipelining
A Hierarchical Parallelizing Compiler for VLIW/MIMD Machines
An Efficient Resource-Constrained Global Scheduling Technique for Syperscalar and VLIW processors
A New Approach to Schedule Operations Across Nested-ifs and Nested-loops
A New Compilation Technique for Parallelizing Loops with Unpredictable Branches on a VLIW Architecture
Architecture of Computing Systems - ARCS 2007: Proc./20th International Conference. Zurich, Switzerland, March 2007
Array Reference Disambiguation for VLIW
A Shape Matching Approach for Scheduling Fine-Grained Parallelism
Automatically Customing VLIW Architectures with Coarse Grained Application-Specific Functional Units
A VLIW Architecture Based on Shifting Register Files
A VLIW Architecture for Optimal Execution of Branch-Intensive Loops
Branch Merging for Effective Explotation of Instruction-Level Parallelism
Code Generation Schema for Modulo Scheduled Loops
Code Positioning for VLIW Architectures
Code Scheduling for VLIW/Superscalar Processors with Limited Register Files
Compiler Techniques for Fine-Grain Execution on Workstation Clusters using PAPERS
Compile Time Optimization of Memory and Register Usage on the Cray 2
Compiling Nested Loops for Limited Connectivity VLIWs
Dynamically Scheduled VLIW Processors
Effective Compiler Support for Predicated Execution Using the Hyperblock
EPIC: Explicitly Parallel Instruction Computing
Exploiting Instruction-Level Parallelism: The Multithreaded Approach
Instruction Scheduling over Regions: A Framework for Scheduling Across Basic Blocks
Integer Loop Code Generation for VLIW
MICRO-25: Proc./The 25th Annual Intern. Symp. on Microarchitecture, Dec.1-4, 1992, Portland, Oregon, USA
Mutation Scheduling: A Unified Approach to Compiling for Fine-Grain Parallelism
Non Homogenous Parallel Memory Operations in a VLIW Machine
Partitioned Register Files for VLIWs: A Preliminary Analysis of Tradeoffs
Pipelining-Dovetailing: A Transformation to Enhance Software Pipelining for Nested Loops
Proposal of a Multi-Threaded Processor Architecture for Embedded Systems and Its Evaluation
Reconfigurable Computing: Architectures, Tools, and Applications: Proc./9th International Symposium, ARC 2013, Los Angeles,CA,USA, March 2013
Register Connection: A New Approach to Adding Registers into Instruction Set Architectures
Register Saturation in Superscalar and VLIW Codes
Retargetable code generation for application-specific processors
Scheduling Non-Numerical Programs with Hierarchical Windows
Sentinel Scheduling for VLIW and Superscalar Processors
Some Design Aspects for VLIW Architectures Exploiting Fine-Grained Parallelism
Speculative Execution Exception Recovery using Write-back Suppression
Static Correlated Branch Prediction
Superblock Formation Using Static Program Analysis
Techniques for Extracting Instruction Level Parallelism on MIMD Architectures
The 16-Fold Way: A Microparallel Taxonomy
The El brus-3 and Mars-M: Recent Advances in Russian High-Performance Computing
The Program Compaction Revisited: the Functional Framework
Using Profile Information to Assist Advanced Compiler Optimization and Scheduling
Using Sacks to Organize Registers in VLIW Machines
VLIW Compilation Techniques for Superscalar Architectures
VLIW Compilation Techniques in a Superscalar Environment
VLIW-машины: развитие архитектуры и принципов построения программного обеспечения
Зависимости по данным в простом и сложном программном конвейере