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Связанные издания:

Evaluation of Release Consistent Software Distributed Shared Memory on Emerging Network Technology
Evaluation of the WM Architecture
EVENODD: An Optimal Scheme for Tolerating Double Disk Failures in RAID Architectures
Expected I-Cache Miss Rates via the Gap Model
Exploring the Design Space for a Shared-Cache Multiprocessor
Extraction of Massive Instruction Level Parallelism
Futurebus + as an I/O Bus: Profile B
HALSIM - A Very Fast SPARC V9 Behavioral Model
Hiding Memory Latency using Dynamic Scheduling in Shared-Memory Multiprocessor
Hierarchical Performance Modeling with MACS: A case Study of the Convex C-240
Impact of Sharing-Based Thread Placement on Multithreaded Architectures
Implementing the NHT-1 Application I/0 Benchmark
Improved Multitheading Techniques for Hiding Communication Latency in Multiprocessor
Improved Parallel I/0 via a Two-phase Tun-time Access Strategy
Improving AP1000 Parallel Computer Performence with Message Communication
Increasing the Number of Strides for Conflict-Free Vector Access
Instruction-level Parallelism in Prolog: Analisis and Architectural Support
Interleaved Parallel Schemes:Improving Memory Throghtput on Supercomputers
Lazy Release Consistency for Software Distributed Shared Memory
Limitations of Cache Prefetching on a Bus-Based Multiprocessor
Limits of Control Flow on Parallelism
Linear Logic and Permutation Stacks - The Forth Shall Be First
Measurement-Based Characterization of Global Memory and Network Contention, Operating System and Parallelization Overheads: Case Study on a Shared-Memory Multiprocessor
Mechanisms for Cooperative Shared Memory
Memory Latency Effects in Decoupled Architectures with a Single Data Memory Module
Memory Management Support for Tiled Array Organization
METRO: A Router Architecture for High-Performance, Short-Haul Routing Networks
Monitoring Program Behaviour on SUPRENUM
Multiple Threads in Cyclic Register Windows
Odd Memory Systems may be quite interesting
On the Attributes of the SCISM Organization
Optimal Allocation of On-chip Memory for Multiple-API Operating Systems
Overview of the Vesta Parallel File System
Parallelising I/0 Intensive Applications for a Workstation Cluster: a Case Study
Parity Logging Overcoming the Small Write Problem in Redundant Disk Arrays
Performance Evaluation for Various Configuration of Superscalar Proessors
Performance of Cached DRAM Organizations in Vector Supercomputers
Performance of the HARRIS RTX 2000 Stack Architecture versus the Sun 4 SPARC and the Sun 3 M68020 Architectures
Performance of the SCI Ring
Performance of Various Computers Using Standard Linear Equations Software
Physical Limitations of a Computer
Prefetch unit for vector operations on scalar computers
Processor Coupling: Integrating Compile Time and Runtime Scheduling for Parallelism
RAID-II: A High-Bandwidth Network File Server
Register Connection: A New Approach to Adding Registers into Instruction Set Architectures
Register Relocation: Flexible Context for Multithreading
Scheduling Parallel I/0 Operations
Secondary Cache Performance in RISC Architectures
Software-Extended Coherent Shared Memory: Performance and Cost
Software Versus Hardware Shared-Memory Implementation: A Case Study