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A Combined Approach to Hardware Verification: Proof-Checking, Rewriting with Decision Procedures and Model-Checking. Part II: Articles
A Combined Approach to Hardware Verification: Proof-Checking, Rewriting with Decision Procedures and Model-Checking. Part I: Slides
A Formal Security Model for Microprocessor Hardware
A Functional Approach for Formalizing Regular Hardware Structures
A Grand Challenge Proposal for Formal Methods: A Verified Stack
A Hardware Design Model for Cryptographic Algorithms
Analysis of a Software/Hardware System by Tense Arithmetic
An Approach to Systems Verification
An Extension of Linear Time Temporal Logic and Its Application to Hardware Design
An Integrated Approach to Hardware/Software Co-design
An Intuitijnistic Modal Logic with Applications to the Formal Verification of Hardware
A Performance Study of Software and Hardware Data Prefetching Schemes
A Petri Net Approach for the Analysis of VHDL Descriptions
Applying Process Technology to Hardware Design
Calculating Digital Counters
Computer Aided Verification: Proc./11th Intern. Conf., CAV 99. Trento, Italy, July 1999
Computer Aided Verification: Proc./14th Intern. Conf., CAV 2002, Copenhagen, Denmark, July 2002
Concurrency and Hardware Design: Advances in Petri Nets
Controlling and sequencing a heavily pipelined floating-point operator
Correct Hardware Design and Verification Methods: Proc./11th IFIP WG 10.5 Advanced Research Working Conf., CHARME 2001, Livingston, Scotland, UK, September 2001
Correct Hardware Design and Verification Methods: Proc./IFIP WG10.2 Advanced Research Working Conf., CHARME 93. Arles, France, May 1993
Data Structure and Algorithms for New Hardware Technology
Degrees of Formality in Shallow Embedding Hardware Description Languages in HOL
Do Object-Oriented Languages Need Special Hardware Support?
Efficient Data Breakpoints
Efficient Hardware/Software Fault Tolerance with Optimistic Execution Policy
Eliminating Higher-Order Quantifiers to Obtain Decision Procedures for Hardware Verification
Embedding Hardware Verification within a Commercial Design Framework
FLEX - семейство аппаратных и программных средств САПР для ПЭВМ
Formal Derivation of Multilayered Hardware/Software Structures
Formal Reasoning on Timing at the Timing Diagram Level
From Programming Language Design to Computer Construction
Functional Modeling of Clocked Hardware Circuits
Ground Temporal Logic: A Logic for Hardware Verification
Hardware and Software Architectures for Fault Tolerance: Experiences and Perspectives
Hardware and Software Synthesis, Optimization, and Verification from Esterel Programs
Hardware and Software: The Closing Gap
Hardware - Software: An Equivalence and a Contradiction
Hardware Support of Object-Oriented Systems
Hardware Verification using Monadic Second-Order Logic
High Performance computer system "Electronica SSBIS"
KARL: A Hardware Description Language as Part of a CAD Toll for VLSI
Layered Modeling of Hardware and Software, with Application to a LAN Extension Router
Linking Higher Order Logic to a VLSI CAD System
Memory Management in Flash-Memory Disks with Data Compression
Model-Based Codesign
Modelling Bit Vectors in HOLL: The Word Library
New Trend and Future Issues of Hardware Description Language and High-Level Synthesis
Obtaining Hardware Performance Metrics for the BlueGene/L Supercomputer
Partial Evaluation of Hardware