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Связанные издания:

16-Bit vs. 32-Bit Instructions for Pipelined Microprocessors
3-d Graphics Processing in Hardware with GLiNT
A Comparison of Modulo Scheduling Techniques for Software Pipelining
Advanced Parallel Processing Technologies: Proc./8th International Symposium, APPT 2009, Rapperswill, Switzerland, August 2009
A Dynamic-Programming Technique for Compacting Loops
A First Step Towards Time Optimal Software Pipelining of Loops with Control Flows
An Experimental Study of an ILP-based Exact Solution Method for Software Pipelining
An Extended Classification of Inter-instruction Dependency and Its Application in Automatic Synthesis of Pipelined Processors
An Integer Linear Programming Model of Software Pipelining for the MIPS R8000 Processor
A Non-Deterministic Scheduler for a Software Pipelining Compiler
A Pipeline Algorithm for Interactive Volume Visualization
Array Reference Disambiguation for VLIW
A Unified Software Pipeline Construction Scheme for Modulo Scheduled Loops
Automatic Generation of Schedulers in the Framework of the PAGODE System
A VLIW Architecture Based on Shifting Register Files
Bidirectional Scheduling: A New Global Code Scheduling Approach
Circular Pipeline: Analysis and Performance Evaluation
Clocked and Asynchronous Instruction Pipelines
Code Generation Schema for Modulo Scheduled Loops
Comparing Software Pipelining for an Operation-Triggered and a Transport-Triggered Architecture
Compiling for Dataflow Software Pipelining
Controlling and sequencing a heavily pipelined floating-point operator
Delayed Exceptions - Speculative Execution of Trapping Instructions
Early Control of Register Pressure for Software Pipelined Loops
Efficient Scheduling of Fine Grain Parallelism in Loops
Efficient State-Diagram Construction Methods for Software Pipelining
Enhanced Modulo Scheduling for Loops with Conditional Branches
Enhanced Regions Scheduling on a Program Dependence Graph
Extending the Rate-Minotonic Scheduling Algorithm to Get Shorter Dalays
Fast Arbitration in Dilated Routers
Formal Verification of Counterflow Pipeline Architecture
Formal Verification of Pipelined Processors
Further Pipelining and Multithreading to Improve RISC Processor Speed. A Proposed Architecture and Simulation Results
Global Software Pipelining with Iteration Preselection
GPMB - Software Pipelining Branch-Intensive Loops
GREO: A Commercial Database Processor Based on A Pipelined Hardware Sorter
Hamiltonian Recurrence for ILP
Implementing Pipelined Computation and Communication in an HPF Compiler
Improved Algorithms for Mapping Pipelined and Parallel Computations
Instruction Scheduling for Complex Pipelines
Languages and Compilers for Parallel Computing: Revised Selected Papers/22nd International Workshop, LCPC 2009, Newark,DE,USA, October 2009
Lifetime-Sensitive Modulo Scheduling
Logic-Based Program Synthesis and Transformation: Revised Selected Papers/19th International Sumposium, LOPSTR 2009, Coimbra, Portugal, September 2009
Mapping Parallel Computations to a Heterogeneous Architecture
Mathematical Model of Pipeline Computation Organization
Maximum Pipelining Linear Recurrence on Static Flow Computers
MIDEE: Smoothing Branch and Instruction Cache Miss Penalties on Deep Pipelines
MT: A Multithreaded 64 Bits RISC CPU
Multidimensional Pipeline and Array Architectures for On-Line Computation of the Fast Orthogonal Transforms
Performance Evaluation of Heuristics for Scheduling Pipelined Multiprocessor Tasks