СТ |
MIRS: Modulo Scheduling with Integrated Register Spilling |
2003 |
Zalamea J., Llosa J., Ayguade E., Valero M. |
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Lecture Notes in Computer Science |
18.06.2003 |
СТ |
Modulo Scheduling with Reduced Register Pressure |
1998 |
Llosa J., Valero M., Ayguade E., Gonzalez A. |
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IEEE Trans. on Computers |
22.08.1998 |
СТ |
Detecting and Using Affinity in an Automatic Data Distribution Tool |
1995 |
Ayguade E., Garcia J., Girones M., Labarta J., Torres J., Valero M. |
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Lecture Notes in Computer Science |
28.03.1995 |
СТ |
Using Sacks to Organize Registers in VLIW Machines |
1994 |
Llosa J., Valero M., Fortes J.A. B., Ayguade E. |
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Lecture Notes in Computer Science |
22.11.1994 |
СТ |
Memory Access Synchronization in Vector Multiprocessors |
1994 |
Valero M., Peiron M., Ayguade E. |
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Lecture Notes in Computer Science |
19.11.1994 |
СТ |
Increasing the Number of Strides for Conflict-Free Vector Access |
1992 |
Valero M., Lang T., Liaberia J. M., Peiron M., Auguade E., Navarro J. J. |
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Computer Architecture News |
24.02.1992 |