|
СТ |
Code Generation Schema for Modulo Scheduled Loops |
1992 |
Rau B. R., Schlansker M. S., Tirumalai P. P. |
|
|
|
SIGMICRO Newsletter |
13.03.1993 |
|
СТ |
EPIC: Explicitly Parallel Instruction Computing |
2000 |
Schlansker M. S., Rau B. R. |
|
|
|
Computer |
07.04.2000 |
|
СТ |
Register Allocation for Software Pipelined Loops |
1992 |
Rau B. R., Tirumalai P. P., Schlansker M. S. |
|
|
|
SIGPLAN Notices |
15.07.1992 |
|
СТ |
Sentinel Scheduling for VLIW and Superscalar Processors |
1992 |
Mahlke S. A., Chen W. Y., Hwu W. W., Rau B. R., Schlansker M. S. |
|
|
|
SIGPLAN Notices |
26.10.1992 |
|
СТ |
Sentinel Scheduling: A Model for Compiler-Controlled Speculative Execution |
1993 |
Mahlke S. A., Chen W. Y., Bringmann R. A., Hank R. E., Hwu W.-M. W., Rau B. R., Schlansker M. S. |
|
|
|
ACM Trans. Computer Systems |
15.02.1994 |
