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Связанные издания:

A Comparison of Modulo Scheduling Techniques for Software Pipelining
A Comparison of Superscalar and Decoupled Access/Execute Architectures
A Comprehensive Instruction Fetch Mechanism for a Processor Supporting Speculative Execution
A Model for Performance Estimation in a Multistreamed Superscalar Processor
An Efficient Resource-Constrained Global Scheduling Technique for Syperscalar and VLIW processors
An Out-of-Order Superscalar Processor with Speculative Execution and Fast, Precise Interrupts
Array Data Flow Analysis for Load-Store Optimizations in Superscalap Architectures
A Trace Cache Microarchitecture and Evaluation
Branch History Table Indexing to Prevent Pipeline Bubbles in Wide-Issue Superscalar Processors
Branch Merging for Effective Explotation of Instruction-Level Parallelism
Code Generation Schema for Modulo Scheduled Loops
Code Scheduling for VLIW/Superscalar Processors with Limited Register Files
Effective Compiler Support for Predicated Execution Using the Hyperblock
Exploiting Instruction-Level Parallelism: The Multithreaded Approach
EXPLORER: A Retargetable and Visualization-Based Trace-Driven Simulator for Superscalar Processors
Hoisting Branch Conditions - Improving Super-Scalar Processor Performance
Improving Semi-Static Branch Prediction by Code Replication
Instruction Scheduling for the Motorola 88110
Integrated Circuit and System Design: Proc./14th International Workshop, PATMOS 2004. Santorini, Greece, September 2004
Limitation of Superscalar Microprocessor Performance
MICRO-25: Proc./The 25th Annual Intern. Symp. on Microarchitecture, Dec.1-4, 1992, Portland, Oregon, USA
Optimization Techniques and Performance Analysis for Different Serial and Parallel RISC-based Computers
Performance Analysis and Design Methodology for a Scalable Superscalar Architecture
Performance Evaluation for Various Configuration of Superscalar Proessors
Performance Evaluation of Instruction Scheduling on the IBM RISC System/6000
Pipelining-Dovetailing: A Transformation to Enhance Software Pipelining for Nested Loops
Precise Compile-Time Performance Prediction for Superscalar-Based Computers
Refined Local Instruction Scheduling Considering Pipeline Interlocks
Resource Allocation in a High Clock Rate Microprocessor
Retargetable Compiler of ANSI C Superset for Vector and Superscalar Computers
Speculative Execution Exception Recovery using Write-back Suppression
StaCS: A Static Control Superscalar Architecture
Superblock Formation Using Static Program Analysis
Techniques for Extracting Instruction Level Parallelism on MIMD Architectures
The Case for a Single-Chip Multiprocessor
The MC88110 Implementation of Precise Exceptions in a Superscalar Architecture
The Program Compaction Revisited: the Functional Framework
Tradeoffs in Processor/Memory Interfaces for Syperscalar Processors
Two-ported Cache Alternatives for Superscalar Processors
VLIW Compilation Techniques in a Superscalar Environment
Walk-Time Address Adjustment for Improving the Accuracy of Dynamic Branch Prediction
Оптимизация кода для суперскалярных процессоров с использованием дизъюнктивных графов
Отображение векторных конструкций языка C[] на векторные и суперскалярные компьютеры (на примере 1860)
Расширение ANSI C для векторных и суперскалярных компьютеров