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IEEE Computer Society Press
Связанные издания:
1992 Publications Catalog IEEE Computer Society Press
8th Workshop on Parallel and Distributed Simulation (PADS 94): Proc./1994 Workshop on Parallel and Distributed Simulation. July 6-8, 1994. Edinburgh, Scotland, U.K.
Abstraction and Performance in the Design of Parallel Programs: An Overview of the SAT Approach
A Comparison of Superscalar and Decoupled Access/Execute Architectures
A Comprehensive Instruction Fetch Mechanism for a Processor Supporting Speculative Execution
A Constructive Approach to Reuse of Conceptual Components
Advances in Software Reuse: Proc./Selected Papers from the Second Intern. Workshop on Software Reusability. Lucca, Italy, March 24-26, 1993
A Dynamic-Programming Technique for Compacting Loops
Analytic Variations on Bucket Selection and Sorting
An Analytic Framework for Specifying and Analyzing Imprecise Requirements
An Efficient Architecture for Loop Based Data Preloading
An Efficient Resource-Constrained Global Scheduling Technique for Syperscalar and VLIW processors
An Evaluation of Bottom-Up and Top-Down Thread Generation Techniques
A New Approach to Schedule Operations Across Nested-ifs and Nested-loops
A New Transformation Method to Generate Optimized DO Loop from FORALL Construct
An Investigation of the Performance of Various Dynamic Scheduling Techniques
An Object-Oriented Implementation of B-ISDN Signalling - Part 2: Extendability Stands the Test
A Non-Deterministic Scheduler for a Software Pipelining Compiler
An Out-of-Order Superscalar Processor with Speculative Execution and Fast, Precise Interrupts
A Reuse Metrics and Return on Investment Model
A Shape Matching Approach for Scheduling Fine-Grained Parallelism
A Specification-Based Adaptive Test Case Generation Strategy for Open Operating System Standards
Asserting Reasoning about Pairwise Transient Interactions in Mobile Computing
Assertion-Oriented Automated Test Data Generation
A VLIW Architecture for Optimal Execution of Branch-Intensive Loops
Branch Merging for Effective Explotation of Instruction-Level Parallelism
Checking Subsystem Safety Properties in Compositional Reachability Analysis
Code Generation Schema for Modulo Scheduled Loops
Code Scheduling for VLIW/Superscalar Processors with Limited Register Files
Controlling and sequencing a heavily pipelined floating-point operator
Data Path Issues in a Highly Concurrent Machine
Design as Evolution and Reuse
Dominator-Path Scheduling - A Global Scheduling Method
Dynamically Scheduled VLIW Processors
Effective Compiler Support for Predicated Execution Using the Hyperblock
Efficient Scheduling of Fine Grain Parallelism in Loops
Effort Estimation Using Analogy
Employing Finite Automata for Resource Scheduling
Enhanced Modulo Scheduling for Loops with Conditional Branches
Enhanced Regions Scheduling on a Program Dependence Graph
Enhanced Reuse with Group Decision Support Systems
Executing Compressed Programs on An Embedded RISC Architecture
Experiences from Application of a Faceted Classification Scheme
Experiences of Software Quality Management Using Metrics through the Life-Cycle
Exploiting Instruction-Level Parallelism: The Multithreaded Approach
Exploting Instruction-Level Parallelism with the Conjugate Register File Scheme
Extraction and Optimization of the Implicit Program Parallelism by Dynamic Partial Evaluation
GPMB - Software Pipelining Branch-Intensive Loops
GRIDS - GRaph-based, Integrated Development of Software: Integrating Different Perspectives of Software Engineering
How to Identify Binary Relations for Domain Models
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