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Связанные издания:

16-Bit vs. 32-Bit Instructions for Pipelined Microprocessors
A case for two-way skewed-associative caches
A Case for Uniform Memory Access Multiprocessors
A Class of Replacement Polices for Medium and High-Associativity Structures
A Comparison of Adaptive Wormhole Routing Algorithms
A Comparison of Dynamic Branch Predictors that use Two Levels of Branch History
A Comparison of Message Passing and Shared Memory Architectures for Data Parallel Programs
A Comparison of Three Current Superscalar Designs
Active Messages:a Mechanism for Integrated Communication and Computation
Adaptive Cach Coherency for Detecting Migratory Shared Data
A graphical comparison of RISK processors
A High-Performance Object-Oriented Memory
A Multithreaded Massively Parallel Architecture
An Adaptive Cache Coherence Protocol Optimized for Migratory Sharing
An Analisys of Loop Latency in Dataflow Execution
An Elementary Processor Architecture with Simultaneous Instruction Issuing from Multiple Theards
An Evaluation Methodology for Microprocessor and System Architectures
A Novel Cache Design for Vector Processing
A Novel Single Instruction Computer Architecture
An Overview of Techniques to Support Continuous Retrieval of Multimedia Objects
A Performance Study of Memory Consistency Models
A Performance Study of Software and Hardware Data Prefetching Schemes
A Process-Dependent Partitioning Strategy for Cache Memories
Architectural Requirements of Parallel Scientific Applications with Explicit Communication
Architectural Support for Performance Tuning: A Case Study on the SPARCcenter 2000
Architectural Support for Translation Table Management in Large Address Space Machines
Architecture and Evaluation of a High-Speed Networking Subsystem for Distributed-Memory Systems
Ariadne - An Adaptive Router for Fault-tolerant Multicomputers
A RISC Processor Architecture with a Versatile Stack System
A Study of I/O System Organizations
A Study of Single-Chip Processor/Cache Organizations for Large Numbers of Transistors
A subclass of Petri Nets as design abstraction for parallel architectures
A Transputer T9000 Family Based Architecture for Parallel Database Machines
A Unified Architectural Tradeoff Methodology
Cache Write Policies and Performance
Characterization of Alpha AXP Performance using TP and SPEC Workloads
Codes to Reduce Switching Transients Across VLSI I/O Pins
Column-Associative Caches: A Technique for Reducing the Miss Rate of Direct-Mapped Caches
Combined Performance Gains of Simple Cache Protocol Extensions
Comparative Performance Evaluation of Cache-Coherent NUMA and COMA Architectures
Complexity/Performance Tradeoffs with Non-Blocking Loads
Compressionless Routing: A Framework for Adaptive and Fault-tolerant Routing
Crosshatch Disk Array for Improved Reliability and Performance
Decoupled Sectored Caches: Conciliating Low Tag Implementation Cost and Low Miss Ratio
Dynamic Dependency Analysis of Ordinary Programs
Dynamic Refresh Method for Dynamic RAMs
Effects of Building Blocks on the Performance of Super-Scalar Architectures
Evaluating Stream Buffers as a Secondary Cache Replacement
Evaluating the Memory Overhead Required for COMA Architectures
Evaluation of Mechanisms for Fine-Grained Parallel Programs in the J-Machine and the CM-5