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SIGMICRO Newsletter

Связанные издания:

A Comparison of Superscalar and Decoupled Access/Execute Architectures
A Comprehensive Instruction Fetch Mechanism for a Processor Supporting Speculative Execution
A Dynamic-Programming Technique for Compacting Loops
An Analysis of Dynamic Scheduling Techniques for Symbolic Applications
An Efficient Architecture for Loop Based Data Preloading
An Efficient Resource-Constrained Global Scheduling Technique for Syperscalar and VLIW processors
An Evaluation of Bottom-Up and Top-Down Thread Generation Techniques
A New Approach to Schedule Operations Across Nested-ifs and Nested-loops
An Extended Classification of Inter-instruction Dependency and Its Application in Automatic Synthesis of Pipelined Processors
An Investigation of the Performance of Various Dynamic Scheduling Techniques
A Non-Deterministic Scheduler for a Software Pipelining Compiler
An Out-of-Order Superscalar Processor with Speculative Execution and Fast, Precise Interrupts
A Shape Matching Approach for Scheduling Fine-Grained Parallelism
A VLIW Architecture Based on Shifting Register Files
A VLIW Architecture for Optimal Execution of Branch-Intensive Loops
Branch History Table Indexing to Prevent Pipeline Bubbles in Wide-Issue Superscalar Processors
Branch Merging for Effective Explotation of Instruction-Level Parallelism
Clocked and Asynchronous Instruction Pipelines
Code Generation Schema for Modulo Scheduled Loops
Code Scheduling for VLIW/Superscalar Processors with Limited Register Files
Control Flow Prediction for Dynamic ILP Processors
Controlling and sequencing a heavily pipelined floating-point operator
Data Path Issues in a Highly Concurrent Machine
Dominator-Path Scheduling - A Global Scheduling Method
Dynamically Scheduled VLIW Processors
Effective Compiler Support for Predicated Execution Using the Hyperblock
Efficient Scheduling of Fine Grain Parallelism in Loops
Employing Finite Automata for Resource Scheduling
Enhanced Modulo Scheduling for Loops with Conditional Branches
Enhanced Regions Scheduling on a Program Dependence Graph
Executing Compressed Programs on An Embedded RISC Architecture
Exploiting Instruction-Level Parallelism: The Multithreaded Approach
EXPLORER: A Retargetable and Visualization-Based Trace-Driven Simulator for Superscalar Processors
Exploting Instruction-Level Parallelism with the Conjugate Register File Scheme
GPMB - Software Pipelining Branch-Intensive Loops
Instruction Scheduling for the Motorola 88110
Interlock Collapsing ALU for Increased Instruction-Level Parallelism
Limitation of Superscalar Microprocessor Performance
Lookhead Scheduling
Measuring Limits of Parallelism and Characterizing Its Vulnerability to Resource Constraints
Microarchitecture Support for Dynamic Scheduling of Acyclic Task Graphs
MIDEE: Smoothing Branch and Instruction Cache Miss Penalties on Deep Pipelines
MISC: A Multiple Instruction Stream Computer
Modifying VM Hardware to Reduce Address Pin Requirements
On the Instruction-Level Characteristics of Scalar-Code in Highly-Vectorized Scientific Applications
On the Limits of Program Parallelism and its Smoothability
Ordering Functions for Improving Memory Reference Locality In a Shared Memory Multiprocessor System
Partitioned Register Files for VLIWs: A Preliminary Analysis of Tradeoffs
Performance Analysis and Design Methodology for a Scalable Superscalar Architecture
Performance Evaluation of Instruction Scheduling on the IBM RISC System/6000