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IEICE Trans.

Связанные издания:

A 400 MFLOPS FFT Processor VLSI Architecture
A 5 ns Embedded RAM for CMOS ASICs and Its Applications to a One-Chip 4096-Channel Time Switch VLSI for Digital Switching Systems
A 64b CMOS Mainframe Execution Unit Macrocell with Error Detecting Circuit
A Constraction of Direct Engagement for Human Interface and Its Prototyping
Activities on Net Theory in Japan
Advanced Traffic Control Techniques for Global Telecommunication Networks
A Factored Reliability Formula for Directed Source-to-All-Terminal Networks
A Fortran Parallelizing Compilation Scheme for OSCAR Using Dependence Graph Analysis
A Hardware Architecture Design Methodology for Hidden Markov Model Based Recognition Systems Using Parallel Processing
A Hierarchical and Dynamic Group-Oriented Cryptographic Scheme
A High Performance 32-Bit Microcontroller for Realtime Applications
A High-Performance Reconfigurable Line Memory Macrocell for Video Signal Processing ASICs
A Japanese Text Dictation System Based on Phoneme Recognition and a Dependency Grammar
A Large Vocabulary Continuous Speech Recognition System with High Predictability
Algebraic Approaches for Nets Using Formulas to Describe Practical Software Systems
A Markovian Imperfect Debugging Model for Software Reliability Measurement
A Master Chip Design of 0.5mm Mixed BiCMOS/CMOS Channelless Gate Array Family
A Model of Neuros with Unidirectional Linear Response
An Access Control Mechanism for Object-Oriented Database Systems
An Analysis of Simulation between Petri Nets through Rewriting Logic
An Automatic Adjustment Method of Backpropagation Learning Parameters, Using Fuzzy Inference
An Effective Application of Net-Theory to Commuication Protocol Development
An Efficient One-Pass Search Algorithm for Parsing Spoken Language
A New Approach for Protocol Synthesis Based on LOTOS
A New Planning Mechanism for Distriburion Systems
A New Version of FEAL, Stronger against Differential Cryptanalysis
An Implementation of a Dialogue Processing System COKIS Using a Corpus Extracted Knowledge
An Intelliigent Cache Memory Chip Suitable for Logical InferOn "inherently context-sensitive" languages - An application
A Petri Net Model for Nonmonotonic Reasoning Based on Annotated Logic Programs
Application of an Improved Genetic Algorithm to the Learning of Neural Networks
Application to Petri Nets to Sequence Control
Applying Distributed Processing Technologies to Intelligent Network
Architecture of a Floating-Point Butterfly Execution Unit in a 400-MFLOPS Processor VLSI and Its Implementation
A Special-Purpose LSI for Inverse Kinematics Computation
A study of Aspect Calculus
A Support Method for Specification Process Based on LTSs
A System for Deciding the Security of Cryptographic Protocols
A Universal Data-Base for Data Compression
A Useful Necessary Conditions and a Simple Sufficient Condition for Liveness of General Petri Nets
Automated Synthesis of Protocol Specifications from Service Specifications with Parallelly Executable Multiple Primitives
Built-In Seltt-Test in a 24 Bit Floatiog Point Digital Signal Processor
Comparison of Syntax-Oriented Spoken Japanese Understanding System With Semantic-Oriented System
Complete Structural Characterization of State Machine Allocatable Nets
Connectionist Approaches to Large Vocabulary Continuous Speech Recognition
Considerations of Learnability of Multilayer Neural Networks
Continuous Speech Recognition Using Two-Level LR Parsing
Coupling of Memory Search and Mental Rotation by a Nonequilibrium Dynamics Neural Network
Deriving Compositional Models for Concurrency Based on de Bakker-Zucker Metric Domain from Structured Operational Semantics
Designing Efficient Geometric Search Algorithms Using Persistent Binary-Binary Search Trees
Design of a Matrix Multiply-Addition VLSI Processor for Robot Inverse Dynamics Computation