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Связанные издания:

Paradigms Admitting Superunitary Behaviour in Parallel Computation
Parallel Algorithm for Inverting Tridiagonal Matrix on Linear Processor Array
Parallel Computing Technologies: Proc./13th International Conference, PaCT 2015, Petrozavodsk, Russia, August 2015
Parallelism and Independence
Parallel Iterated Normalized Backprojection
Parallel Processing: CONPAR 92 - VAPP V: Proc./Second Joint Intern. Conf. on Vector and Parallel Processing. Lyon, France, September 1992
Parallel Task Assignment by Graph Partitioning
PARLE 94 Parallel Architectures and Language Europe: Proc./6th Intern. PARLE Conf. Athens, Greece, July 1994
Partial Evaluation for Scientific Computing: The Supercomputer Toolkit Experience
Partitioning & Mapping Problems in Heterogeneous Computing
Performance Evaluation and Benchmarking: Revised Selected Papers/12th TPC Technology Conference, TPCTC 2020, Tokyo, Japan, August 2020
Performance Evaluation for Various Configuration of Superscalar Proessors
Performance Evaluation of Instruction Scheduling on the IBM RISC System/6000
Performance of Cached DRAM Organizations in Vector Supercomputers
POMP or How to design a massively parallel machine with small developments
Prefetch unit for vector operations on scalar computers
Processor Allocation Policies for Message-Passing Parallel Computers
Processor Coupling: Integrating Compile Time and Runtime Scheduling for Parallelism
Processor Element Architecture for a Parallel Inference Machine, PIM/p
Process Scheduling in DSC and the Large Sparse Linear Systems Challenge
Programming Languages Specification and Prototyping Using the MAX System
Programming with Actors: State-of-the-Art and Research Perspectives
Promises and Issues in Optical Computing
Prophetic Branches: A Branch Architecture for Code Compaction and Efficient Execution
Proposal of a Multi-Threaded Processor Architecture for Embedded Systems and Its Evaluation
Quattro Pro 4.0- новый ход корпорации Borland
Quick Atomic Broadcast
Real-Number Codes for Fault-Tolerant Matrix Operations On Processor Arrays
Reconfigurable Computing: Architectures, Tools, and Applications: Proc./9th International Symposium, ARC 2013, Los Angeles,CA,USA, March 2013
Reducing Network Hardware Quantity by Employing Multi-Processor Cluster Structure in Distributed Memory Parallel Processors
Register Connection: A New Approach to Adding Registers into Instruction Set Architectures
Representation of the Gabow Algorithm for Finding Smallest Spanning Trees with a Degree Constraint on Associative Parallel Processors
Retargetable code generation for application-specific processors
RISC-процессоры
Scalable parallel subdefinite calculations for sparse systems of constraints
Scaling-up Model-Based Troubleshooting by Exploiting Design Functionalities
Sense of Direction in Processor Networks
Sentinel Scheduling for VLIW and Superscalar Processors
Software Products International Presents the Open Access II Demo Tutorial
Software Support for Parallel Computing: Where Are We Headed?
Solving the generalized eigenvalue problem on a synchronous linear processor array
Sparcle: A Multithreaded VLSI Processor for Parallel Computing
Static and Dynamic Processor Allocation for Higher-Order Concurrent Languages
Stochastic Scheduling With Variable Profile and Precedence Constraints
Stride Directed Prefetching in Scalar Processors
Structuring modelling knowledge for CASE shells
SuperCalc5 - табличный процессор нового поколения
Supercomputing Frontiers: Proc./6th Asian Conference, SCFA 2020, Singapore, February 2020
SWIFT - a New Symbolic Processor
Synthesis of a new Systolic Architecture for the Algebraic Path Problem