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Связанные издания:

16-Bit vs. 32-Bit Instructions for Pipelined Microprocessors
A 64-bit RISC Microprocessor for Parallel Computer Systems
A graphical comparison of RISK processors
A Layered Real-Time Specification of a RISC Processor
Alpha и омега компьютерной технологии 21-го века
A Microcode Compiler for the Watch-oriented RISC Processor
A Modular Approach to Motorola PowerPC Compilers
A Multithreaded Implementation of Id using P-RISC Graphs
A Non-Branch Risc Kernel for Large-Grain Dataflow Computation
A Process-Dependent Partitioning Strategy for Cache Memories
A Review of AIX APL2 for the RISC System/6000
Arhitecture of an AI Processor Chip (IP 1704)
A RISC Based Protocol Converter, Printer Emulator for IBM 3270 Environment
A RISC Processor Architecture with a Versatile Stack System
Binary Translation
Compile Time Optimization of Memory and Register Usage on the Cray 2
Costs and Benefits of Multithreading eith Off-the-Shelf RISC Processors
Design of the Dataflow Single-Chip Processor EMC-R
Enhanced Code Compression for Embedded RISC Processors
Executing Compressed Programs on An Embedded RISC Architecture
Experience with a Software-Defined Machine Architecture
Extending RICS-CLP(Real) to Handle Symbolic Functions
Further Pipelining and Multithreading to Improve RISC Processor Speed. A Proposed Architecture and Simulation Results
Hardware and Software Support for Efficient Exception Handling
History of the PowerPC Architecture
Implementational Issues for Verifying RISC-Pipeline Conflicts in HOL
Implementing a Methodology for Formally Verifying RISC Processors in HOL
Metaclasses and Their Applications
Migrating a CISC Computer Family onto RISC via Object Code Translation
MMIXware: A RISC Computer for the Third Millennium
Monash Secure RISC Multiprocessor: Performance Simulation
Multiple Threads in Cyclic Register Windows
Optimization Techniques and Performance Analysis for Different Serial and Parallel RISC-based Computers
PA-RISC to IA-64: Transparent Execution, No Recompilation
PCs and Workstations
Performance of the HARRIS RTX 2000 Stack Architecture versus the Sun 4 SPARC and the Sun 3 M68020 Architectures
Porting OpenVMS from VAX to Alpha AXP
Proc./Intern. Workshop on High-Level Computer Architecture 84. May 21-25, 1984
RISC PC - что нас ждет
RISC-y Business
RISC- и CISC-процессоры для встроенных систем
RISC-процессоры
RISC-процессоры: сравнительный анализ
RISC ЦП следую его поколения
RTSM - A Runtime System for Transputer based Realtime Systems
Scheduling Time-Critical Instructions on RISC Machines
Secondary Cache Performance in RISC Architectures
The Interactive Development and Testing System for a RISC-Style Processor
The Performance Evaluation of a 64b Microprocessor with a Two Level Cache
The PowerPC 603 Microprocessor